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Semester 1

Digital System Design and Digital Systems Laboratory 3 (ELEE09035)

Subject

Electronics and Electronic Engineering

College

SCE

Credits

20

Normal Year Taken

3

Delivery Session Year

2023/2024

Pre-requisites

Knowledge of basic digital circuit theory.

Course Summary

This course aims to build on the material presented in second year and to give the students an intuitive feel for the basic building blocks of digital systems.The lecture course seeks to enhance student understanding of digital system design. The course provides an introduction to hardware description languages, a broad overview of programmable logic devices and further illustration of data path / controller model design examples. There is a focus on adder and multiplier architectures and computer arithmetic. A Reduced Instruction Set Computing (RISC) microprocessor architecture is outlined. Verification of digital systems is introduced.The purpose of this laboratory course is to produce students who are capable of developing synchronous digital circuits from high level functional specifications and prototyping them on FPGA hardware using a standard hardware description language (HDL).

Course Description

Lecture course:Logic design fundamentals. State machines, equivalent states and state reduction. Implication charts.Introduction to hardware description languages (HDL). Synthesis. Behavioural, structural and data flow (register-transfer level, RTL) models.Programmable logic devices. Simple programmable logic devices, complex programmable logic devices, field programmable gate arrays, programmable SoCs.Design examples using data path, controller model. Adders. Critical path, carry-lookahead adder, parallel prefix adder.Multipliers. Add and shift multiplier, array multiplier. Signed integer/fraction multiplier.State machine charts. Microprogramming.Design translation (Synthesis). Mapping, placement and routing.Floating point arithmetic. Multiplication and addition.Introduction to design of RISC microprocessors.Introduction to verification of digital systems. Functional verification. Timing verification.Laboratory:Week 1: Hello world & Hello lots of worldsWeek 2: Hello synchronous world & shifting the worldWeek 3: Shifting many worlds & counting the worldWeek 4: Timing the world & decoding the worldWeek 5: Timing the world in decimal & Colour the worldWeek 6: Colour the worldWeek 7: Assessment 1Week 8: World of state machines & World of linked state machinesWeek 9: World of linked state machines & Snake gameWeek 10: Snake gameWeek 11: Assessment 2

Assessment Information

Written Exam 50%, Coursework 50%, Practical Exam 0%

Additional Assessment Information

Written exam: 50%Coursework: 50%

view the timetable and further details for this course